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BTA Design Services Inc.: Senior Fpga Designer

BTA Design Services Inc.

This is a Full-time position in Gatineau, QC posted February 17, 2021.

We’re hiring!

Come and join one of the fastest growing design services companies in Ottawa.

Be part of a company that offers interesting work in challenging, stimulating technical environments with companies that lead the world in technology and innovation.BTA Design Services is searching for Senior FPGA Designers.

We recognize that our strength is in the individuals who bring their talents with them to work so at BTA Design Services, we foster an environment where everyone on the team is appreciated, trusted and engaged.

We also recognize that work-life balance is important and we strive to provide our employees not just with challenging roles but with roles that also allow them to enjoy family, friends and life outside of work.As our ideal candidate, you’re a dynamic and collaborative designer who’s easy to work with, quick to learn, and keen to solve tough technical problems.

You’re skilled in System Verilog, with significant experience working in the ASIC/FPGA Design Field within the telecom/datacom domain.Duties & ResponsibilitiesUnderstand high-level requirements and system architecture and translate them into detailed FPGA device architectures.Interface with and offer leadership to the FPGA design team, hardware team and software team.Design and implement RTL logic (mainly Verilog or System Verilog), run block-level simulation, FPGA synthesis and backend, timing closure.Perform lab bring-up, product integration and support.Interface with the verification team, hardware team and support team.RequirementsThe ideal individual is a senior/staff/principal FPGA Design Engineer with the following: Minimum of an undergraduate degree in EE or equivalent skills/experience.7+ years of relevant experience.Experience with modern FPGA development and tools including logic design, synthesis, PnR and timing closure.Experience with high-speed FPGA Design Flow using Verilog and Xilinx Vivado.Experience with complex asynchronous clock boundaries & high-speed serial interfaces.Track record as a self-starter, a team player and a leader.In addition to experience in one or more of the following:Architecture and design of digital cellular radio and RANs or Base Stations.Experience with modern cellular radio standards (e.G.

5G, 4G, LTE, 3GPP, O-RAN).DSP algorithm design and implementation in DSP devices or FPGAs.Fronthaul/midhaul connectivity, eCPRI, CPRI, 10G+ Ethernet, optical networking.CPU, GPU, NPU, DSP processor sub-system design or integration.